The prior art typically forms a fixed voltage from a voltage divider. The fixed voltage serves as an on-chip reference voltage. For example, as shown in FIG. 5, voltage divider 51 provides a reference voltage V.sub.ref 52 to comparator 53. When the input signal, V.sub.IN 54, exceeds the reference voltage V.sub.ref 52, the comparator 53 will trigger and change the output signal 55, typically from low to high. The voltage divider 51 forms V.sub.ref 52 from V.sub.TT 57. The arrangement 50 is typically used as single-ended receiver circuit, with V.sub.DD 56 being an on chip power supply voltage, while V.sub.IN 54 is an off chip signal. The internal arrangement of the voltage divider 51 typically comprises two nFET transistors with the source of the first one tied to the drain of the second. The drain of the first FET is tied to V.sub.TT 57, and the source of the second FET is tied to ground. The gates of both FETS are connected to V.sub.DD 56. Note that for proper operation V.sub.DD &gt;V.sub.TT +FET threshold voltage. The FETs are sized to produce the required reference voltage, i.e. V.sub.ref 52. The voltage divider could also use PVT (process, voltage, temperature) compensation to attempt to minimize drift from changes in process, power supply voltage V.sub.DD, or temperature, and thereby make the reference voltage more stable. Note that a voltage divider may also be formed from two pFETs in series or from a circuit comprising a pFET connected to V.sub.TT and a nFET connected to ground.
Another approach of the prior art is to produce the reference voltage off chip using two discrete resistors. The reference voltage is then brought on chip through at least one pin. However, this approach requires the signal to be routed along the PC board, which introduces noise into the reference voltage signal. If higher capacitive route is used requiring either wide traces or bypass capacitors, then the noise is reduced. However, cleaner power distribution mechanisms may reduce the area available for other mechanisms. Note that the large area forms a capacitance with the ground plane that stabilizes the signal. Using pins to bring the signal on chip also introduces noise into the reference signal. If more pins are used, then the noise is reduced. However, the more pins that are used for the reference voltage, reduces the number of pins available for other signals. Note that a high pin count stabilizes the signal by reducing loop inductance. Thus, these two trades offs make this approach undesirable.
Noise tolerance is a problem with arrangement 50. Ringing or other noise would cause the V.sub.IN 54 input signal to cross the reference voltage V.sub.ref 52. Thus, the comparator would inadvertently trip, and possibly send an incorrect signal onto other portions of the chip. Note that noise can be caused by crosstalk, such that another signal couples with the input signal line V.sub.IN 54. Other noise can be caused by reflections from impedance mismatch from different media connections.
FIGS. 6A-6D depict the effects of noise on the arrangement of FIG. 5. Each of the graphs of FIGS. 6A-6D depict various voltages of the arrangement of FIG. 5 at a common reference time. Note that the time line is in nanoseconds. The off chip signal 57 is the signal generated by an off chip (i.e. off of the comparator chip) device. The off chip driving signal is the signal sent by the driving circuit of the off chip device. Note the noise introduced by the transmission line effects. This signal, which is received by the receiving circuitry, V.sub.IN 54, is replete with noise when compared with off chip signal 57. Some of the noise spikes are above the reference voltage V.sub.ref 52. Spikes 61 and 62 are high enough to the comparator output signal 55 to exceed the receiver latch threshold voltage 59, as shown by 61' and 62'. Thus, the noise has caused erroneous signals to be propagated through the receiving chip.
The prior art has attempted to solve this problem by constructing the comparator with a built-in hysteresis mechanism, using feedback. The hysteresis comparator has the values of the FETs inside the comparator changed from a standard comparator. In a standard comparator, there are two branches, one connected to the positive input and one connected to the negative input. The FET sizes, connected to both the positive input and the negative input, are closely matched. If the positive and negative inputs are identical, then the currents going through are equal. When there is the slightest difference between the positive and the negative inputs, the comparator will switch to whichever branch has the higher gate voltage. If the FET sizes are changed, then the currents are thrown off balance and therefore, create an unevenness as to where the output will switch. Thus, the comparator will switch with some offset. In order for the output of the comparator to switch, a greater change in the input signal is required, e.g. if the signal is low and the threshold has been increased, then the input signal must go slightly above the original threshold voltage before the comparator will trip. This provides some measure of tolerance of noise, and prevents improper comparator tripping.
However, this solution has several disadvantages. First, the design of the hysteresis comparator is not portable. Each comparator would have be constructed with different elements, reflecting the different input signals, as well as the different operations of the output signals. Moreover, in some instances hysteresis is not desired, particularly when a true differential receiver is required. Thus, multiple comparators would have to be designed and constructed on each chip device.
Therefore, there is a need in the art for a hysteresis mechanism that provides noise tolerance and does not require each individual receiver or comparator to be specifically modified. Moreover, there is a need in the art for a mechanism to disable hysteresis when it is not needed.